Sr. Principal Design Engineer – Cadence
Location: Av Contorno 5800, Belo Horizonte, Minas Gerais, Brazil. Full‑time, 40 hours/week.
Job Description
Work with ASIC Design Verification flow.
Daily activities related with Simulation DV, Emulation, Post Silicon Bringup Validation.
Requirements
Complete Bachelor's degree in Electrical Engineering, Computer Science or related areas.
Strong expertise in building test‑benches using System‑Verilog, UVM, C/C++.
Strong digital logic fundamentals and understanding.
Experience in functional coverage/code coverage/assertions (SVA) development and closure.
Strong debug skills.
Should have gone through complete lifecycle of ASIC productization.
Experience in using emulation or post silicon desirable but not mandatory.
Proficient in scripting/automation using any standard scripting language like Perl/Python etc.
Excellent verbal and written communication skills and a good team player.
Additional Job Details
Employment category: CLT.
Employment term: 40 hours/week.
Competitive benefits.
Seniority level: Mid‑Senior level.
Employment type: Full‑time.
Job function: Engineering and Information Technology.
Industries: Software Development.
Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play. Our products are used in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments.
We're doing work that matters. Help us solve what others can’t.
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